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| ICS601-02 Low Phase Noise Clock Multiplier Description The ICS601-02 is a low cost, low phase noise, high performance clock synthesizer for any application that requires low phase noise and low jitter. The ICS601 is ICS' lowest phase noise multiplier. Using ICS' patented analog and digital Phase Locked Loop (PLL) techniques, the chip accepts a 10-27 MHz crystal or clock input, and produces output clocks up to 170 MHz at 3.3 V. A separate supply pin is provided so that the output can be 2.5 V. This product is intended for clock generation. It has low output jitter (variation in the output period), but input to output skew and jitter are not defined nor guaranteed. For applications which require defined input to output timing, use the ICS670-01. Features * Packaged in 16 pin SOIC (Pb free) * Uses fundamental 10 - 27 MHz crystal, or clock * Patented PLL with the lowest phase noise * Output clocks up to 170 MHz at 3.3 V * Low phase noise: -132 dBc/Hz at 10 kHz * Output Enable function tri states outputs * Low jitter - 18 ps one sigma * Full swing CMOS outputs with 25 mA drive capability at TTL levels * Advanced, low power, sub-micron CMOS process * Industrial temperature * 3.3 V or 5 V core VDD. Output clock can operate down to 2.5 V Block Diagram VDD VDDP Reference Divide Phase Comparator Charge Pump Loop Filter VCO Output Buffer CLK X1/ICLK Crystal Oscillator X2 ROM Based Multipliers VCO Divide Optional crystal capacitors needed for accurate tuning (not shown) MDS 601-02 D GND S3 S2 S1 S0 OE 1 Revision 111204 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose * CA*95126 * (408) 295-9800tel * www.icst.com ICS601-02 Low Phase Noise Clock Multiplier Pin Assignment CLK VDDP VDD VDD VDD X2 S1 X1/ICLK 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GND GND GND GND OE S0 S3 S2 Multiplier Select Table S3 S2 S1 S0 CLK (see note 2 on following page) 0 0 0 0 Input x4/3 0 0 0 1 Input x4 0 0 1 0 Input x25/4 0 0 1 1 Input x3 0 1 0 0 Input x7.5 0 1 0 1 Input x5 0 1 1 0 Input x6 0 1 1 1 Input x8 1 0 0 0 Input x8/3 1 0 0 1 Input x8 1 0 1 0 Input x12.5 1 0 1 1 Input x6 1 1 0 0 Input x15 1 1 0 1 Input x10 1 1 1 0 Input x12 1 1 1 1 Input x16 0=connect directly to ground 1=connect directly to VDD Pin Descriptions Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name CLK VDDP VDD VDD VDD X2 S1 X1/ICLK S2 S3 S0 OE GND GND GND GND Type O P P P P XO I XI I I I I P P P P Description Clock output from VCO. Output frequency equals the input frequency times multiplier. Supply pin for CLK output buffer. Sets output clock amplitude. Connect to 2.5V or 3.3V Connect to +3.3V or +5V. Must match other VDDs. Connect to +3.3V or +5V. Must match other VDDs. Connect to +3.3V or +5V. Must match other VDDs. Crystal connection. Connect to a 10 - 27 MHz fundamental parallel mode crystal. Multiplier select pin 1. Determines CLK output per table above. Internal pull-up. Crystal connection. Connect to a 10-27 MHz fundamental parallel mode crystal, or clock. Multiplier select pin 2. Determines CLK output per table above. Internal pull-up. Multiplier select pin 3. Determines CLK output per table above. Internal pull-up. Multiplier select pin 0. Determines CLK output per table above. Internal pull-up. Output Enable. Tri-states the output clock when low. Internal pull-up. Connect to ground. Connect to ground. Connect to ground. Connect to ground. Key: I = Input with internal pull-up resistor; O = output; P = power supply connection; XI, X2 = crystal connections. MDS 601-02 D 2 Revision 111204 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose * CA*95126 * (408) 295-9800tel * www.icst.com ICS601-02 Low Phase Noise Clock Multiplier Achieving Low Phase Noise Figure 1 shows a typical phase noise measurement in a 125 MHz system. There are a few simple steps that can be taken to achieve these levels of phase noise from the ICS601-02. Variations in VDD will increase the phase noise, so it is important to have a stable, low noise supply voltage at the device. Use decoupling capacitors of 0.1 F in parallel with 0.01 F. It is important to have these capacitors as close as possible to the ICS601-02 supply pins. Disabling the REFOUT clock is also important for achieving low phase noise; lab tests have shown that this can reduce the phase noise by as much as 10 dBc/Hz. 0 -20 -40 Phase Noise (dBc/Hz) -60 -80 -100 -120 -140 10.0E+0 100.0E+0 1.0E+3 10.0E+3 100.0E+3 1.0E+6 10.0E+6 Offset from Carrier (Hz) Figure 1. Phase Noise of ICS601-02 at 125 MHz out, 25 MHz crystal input, VDD = 3.3 V. External Components/Crystal Selection The ICS601-02 requires a minimum number of external components for proper operation. Decoupling capacitors of 0.01 F and 0.1 F should be connected between VDD and GND, as close to the part as possible. A series termination resistor of 33 may be used for the clock output. The crystal must be connected as close to the chip as possible. The crystal should be fundamental mode, parallel resonant. Do not use third overtone. For exact tuning when using a crystal, capacitors should be connected from pins X1 to ground and X2 to ground. In general, the value of these capacitors is given by the following equation, where CL is the crystal load capacitance: Crystal caps (pF) = (CL -5) x 2. So for a crystal with 16 pF load capacitance, two 22 pF caps can be used. For any given board layout, ICS can measure the board capacitance and recommend the exact capacitance value to use. MDS 601-02 D 3 Revision 111204 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose * CA*95126 * (408) 295-9800tel * www.icst.com ICS601-02 Low Phase Noise Clock Multiplier Electrical Specifications Parameter Conditions Minimum ABSOLUTE MAXIMUM RATINGS (note 1) Supply voltage, VDD Referenced to GND Inputs and Clock Outputs Referenced to GND -0.5 Ambient Operating Temperature, I version Industrial temperature -40 Soldering Temperature Max of 10 seconds Storage temperature -65 DC CHARACTERISTICS (VDD = VDDP = 3.3 V unless noted) Operating Voltage, VDD 3.0 Output Buffer Voltage, VDDP 2.375 Input High Voltage, VIH, X1/ICLK pin only Note 3 (VDD/2)+1 Input Low Voltage, VIL, X1/ICLK pin only Note 3 Input High Voltage, VIH 2 Input Low Voltage, VIL Output High Voltage, VOH, CMOS level IOH=-4mA VDD-0.4 Output High Voltage, VOH IOH=-12mA 2.4 Output Low Voltage, VOL IOL=12mA Operating Supply Current, IDD No Load, 125 MHz Short Circuit Current Each output 40 Input Capacitance OE, select pins AC CHARACTERISTICS (VDD = VDDP = 3.3 V unless noted) Input Frequency 10 Output Frequency at 3.3V or 5V Output Clock Rise Time 0.8 to 2.0V, no load Output Clock Fall Time 0.8 to 2.0V, no load Output Clock Duty Cycle At VDD/2 45 Maximum Absolute Jitter, short term, 125 MHz No load Maximum Jitter, one sigma, 125 MHz (x5) No load Phase Noise, relative to carrier, 125 MHz (x5) 100 Hz offset Phase Noise, relative to carrier, 125 MHz (x5) 1 kHz offset Phase Noise, relative to carrier, 125 MHz (x5) 10 kHz offset Phase Noise, relative to carrier, 125 MHz (x5) 100 kHz offset Typical Maximum 7 VDD+0.5 85 260 150 5.5 VDD (VDD/2)-1 0.8 Units V V C C C V V V V V V V V V mA mA pF MHz MHz ns ns % ps ps dBc/Hz dBc/Hz dBc/Hz dBc/Hz 9 60 5 0.4 20 50 50 18 -108 -123 -132 -125 27 170 1.5 1.5 55 75 25 Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability. 2. The phase relationship between input and output can change at power up. For a fixed phase relationship, see the ICS570 or ICS670. 3. Switching occurs nominally at VDD/2. MDS 601-02 D 4 Revision 111204 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose * CA*95126 * (408) 295-9800tel * www.icst.com ICS601-02 Low Phase Noise Clock Multiplier Package Outline and Package Dimensions (For current dimensional specifications, see JEDEC no. 95.) 16 pin SOIC Inches Symbol Min Max A 0.0532 0.0688 A1 0.0040 0.0098 B 0.0130 0.0200 C 0.0075 0.0098 D 0.3859 0.3937 E 0.1497 0.1574 e .050 BSC H 0.2284 0.2440 h 0.0099 0.0195 L 0.0160 0.0500 Millimeters Min Max 1.35 1.75 0.10 0.24 0.33 0.51 0.19 0.24 9.80 10.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.41 1.27 E INDEX AREA H D A1 e C h x 45 A L B Ordering Information Part/Order Number ICS601M-02I ICS601M-02IT ICS601M-02ILF Marking ICS601M-02I ICS601M-02I ICS601M-02IL Shipping packaging tubes tape and reel tubes Package 16 pin narrow SOIC 16 pin narrow SOIC 16 pin narrow SOIC Temperature -40 to 85 C -40 to 85 C -40 to 85 C -40 to 85 C ICS601M-02ILFT ICS601M-02IL tape and reel 16 pin narrow SOIC While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. MDS 601-02 D 5 Revision 111204 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose * CA*95126 * (408) 295-9800tel * www.icst.com |
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